NAND type EEPROMs (Electrically Erasable Programmable Read Only Memories) or flash memories have been developed for solid-state mass storage applications for portable music players, mobile telephones, digital cameras, and the like, as well as have been considered as a replacement for hard disk drives (HDDs).
Referring to FIG. 1, a circuit diagram of an electrically erasable programmable read-only memory is shown comprising an array of memory cells, which is formed on a chip substrate. As will be recognized by those in the art, FIG. 1 is a circuit diagram of a portion of a NAND flash memory array. Various components, such as column and row decoders, sense circuitry and other control circuitry are not shown but are familiar to those in the art.
An exemplary memory array is partitioned into many memory “blocks.” Each block has several “pages.” A page has many memory “cells.” For example, a 1 Gb memory has 1024 blocks, and one block has 64 pages. Each page has 2K bytes of bits (i.e., 16K bits). A word line contains a page or multiple pages. A cell string or two cell strings are provided per block in the bit line direction. A cell string has 16 bits, 32 bits or
The illustrated memory array of FIG. 1 includes a plurality of parallel bit lines BL1, BL1, BL2 . . . through BLn coupled to memory cells defined at intersections of individual bit lines and word lines of the memory array. In the illustrated memory, the individual cells are floating gate flash cells, although other cell structures, such as SONOS or split gate flash cells are used in some EEPROMs. Parallel word lines WL0, WL1, WL2 . . . WL15 are formed over the substrate so as to form control gates for the individual flash memory cells. Selection transistors are associated with each bit line and are coupled to signals SS and GS.
Block select signal BK is used to select a block of memory cells and bias the gate terminal of the NMOS pass/driving transistors. The driving transistors receive global word line signals GWL0, GWL1, . . . through GWL15, respectively, at their drain terminals for biasing word lines WL0 to WL15, respectively, during program and erasing. CS designates the common source line. A cell string is connected to a bit line through SS selection transistor on one side and to CS through the GS transistor.
The tables of FIG. 1 show the program and erase conditions for the flash memory of FIG. 1. The erase conditions are of particular note. During erasure, all of the word lines in a string of the selected block are grounded and the cell well voltage (VW) is raised to about 20V. This large voltage difference forces the electrons stored in the floating gate to escape into the cell well. The unselected blocks share the common cell well with the selected block, which is biased at the high voltage. The corresponding word lines in the unselected block are floating. Since the coupling factor between the cell well and the floating control gate (i.e., the floating word line) has been reported at about 98%, the word line voltage of these unselected blocks is coupled to about the voltage level of the cell well (the P well of the NMOS memory cells), i.e., about 20V. The corresponding word line pass transistors of these unselected blocks are turned off, as select signal BK is set to 0V for the unselected block. The driving transistors of the unselected blocks, therefore, experience about a 20V stress from source node (i.e., the word line voltage node) to the gate node (i.e., the block select node). If the gate oxide thickness of the pass transistors is about 300 Å, then the resulting electrical field is about 6.7MV/cm (20V/300 Å), which produces reliability concerns for the high density NAND flash. For example, in current 1 Gbyte NAND flash devices have 1024 blocks, 64 pages per block, two pages per word line, and each word line divided into two lines to reduce RC delay, there are 64K driver transistors (1024×32×2) that can be stressed.
Therefore, there remains a need for an improved flash memory erase procedure, as well as an improved flash memory, that considers the voltage stress on the driving transistors of unselected blocks.